Celero Communications announced a $275 million Series C on September 8 for chips that help move data among AI computers. The Irvine, California company designs digital signal processors, or DSPs, for optical connections inside and between data centers. Its technology is aimed at infrastructure builders trying to make large groups of AI processors work together without the network becoming the limiting factor.
A large AI workload can involve processors spread across racks or even separate buildings. Those machines need to exchange information, not simply calculate independently. Optical equipment carries the data over fiber, with signal-processing chips helping prepare and recover the information carried by light. Celero's product sits in that communications layer; it is not another processor for running an AI model itself.
The company's approach uses coherent optics, a form of transmission that combines sophisticated signal processing with ways of carrying more information over the same fiber. Coherent systems already serve telecommunications networks, but Celero argues that equipment designed for long-distance telecom links carries unsuitable power, delay and cost tradeoffs for dense AI infrastructure. It is designing the digital processor and the accompanying analog circuitry around those data-center requirements.
Celero says it has validated its design in 2-nanometer silicon and is developing a path from 1.6-terabit to 3.2-terabit optical connections. CapitalG separately describes the design milestone and the need to connect increasingly large groups of accelerators. These statements concern the technology's development, not a disclosed volume-shipment record. The founders, Nariman Yousefi and Oscar Agazzi, previously worked in optical networking and signal processing at companies including Inphi and Marvell.
Atreides Management, Valor Equity Partners and CapitalG led the round, with participation from Sutter Hill Ventures and Maverick Silicon. Celero says the financing values it above $3 billion and brings total capital raised to $415 million. The new round will support research, the product roadmap and production readiness. CapitalG had led its $100 million Series B in November 2025.
For a data-center operator, the useful outcome would be more capacity and reach without an unacceptable increase in networking power or cost. Celero now has to turn a validated chip architecture into components that can be manufactured, integrated and operated reliably. That transition matters because adding more AI processors does not solve a communications bottleneck if those processors cannot exchange data efficiently.